JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.

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All components used for this testing must be daisy-chained. The drop table shall then be raised to the height specified according to JEDEC condition and dropped on the strike surface while measuring the G level, pulse duration, and pulse shape. Drop testing on other board orientation is not required but may be performed if deemed necessary. A visible partial separation of component from jesv22 test board, even without a significant increase in resistance or intermittent discontinuity, shall also be considered as a n111.

The method is applicable to both area-array and perimeter-leaded surface mounted packages. The board assembly shall then be mounted on the drop test fixture using four screws. The boards shall be symmetric in construction about the mid-plane of the board, except for the minor differences in the top and bottom two layers.

The free-fall drop height of jed22 drop table needed to attain the prescribed peak acceleration and pulse duration.

For example, a 9 x 9 pad array can be designed to accommodate suitably designed daisy chain components with 8 x 8, 7 x 7, 8 x 9, or any other ball array combination. At least one board shall be used to adjust board mounting process such as paste printing, placement, and reflow profile. Organizations may obtain permission to reproduce a limited number of copies through entering into v111 license agreement.

Experience with different board orientation has suggested that the horizontal b111 orientation with components facing down results in maximum PCB flexure and, thus, the worst orientation for failures. Plated through holes or edge fingers shall be provided on each end of the board for soldering wires, one for each side b11 and bottom of the board.

JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. The bottom of the drop table is usually rounded slightly to ensure very small area of contact with jess22 strike surface. This can occur if the PCB traces come off the board with component while maintaining electrical continuity.


The comparability between different test sites, data acquisition methods, and board manufacturers has not been fully demonstrated by existing data. As wires soldered to the board for electrical continuity test may also come off during the test, it is highly recommended that all electrical connections be checked once a failure in indicated to ensure that the failure is due to component to board interconnection failure.

The selection of packages should cover different locations on the board. These handheld electronic products are more prone to being dropped during their useful service life because of their size and weight.

It should be noted, however, that any additional mass will add significant dynamic weight to the board and may alter its dynamic response. Therefore, options are provided for mounting just 1 or 5 components on the board using the following locations: The additional data shall directly compare the effect of optional component mounting 1 or 5 components to the preferred component mounting configuration.

A packaged semiconductor device. Although daisy-chain nets will typically not require plated though holes PTH other than those required for manual probe pads and connectors, the test board shall contain PTH in the component region 1. jessd22

Means shall be provided in the apparatus such as automatic braking mechanism to eliminate bounce and to prevent multiple shocks to the board. The high-speed data acquisition system should be able to measure resistance with a sampling rate of 50, samples per second or greater.

Smaller clearance can be used as long as it does not cause any solder mask encroachment on pads due to misregistration. The daisy chain should either be done at the die level or by providing daisy chain links at the lead-frame or substrate level.

Sample sizes greater than specified below can be used to generate statistically sufficient data. This shall be accomplished by designing double sided boards with mirror component footprint on each side top and bottom of the board. The primary driver of these failures is excessive flexing of circuit board due to input acceleration to the board created from dropping the handheld electronic product.


The capture pad diameter shall be at least microns. Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Electrical continuity test jdsd22 also be performed on all mounted units to jesd22 any opens or shorts. Additional strain gages may also be mounted at different locations on the board to fully characterize the strain response of the assembly. However, this is an additional test option and not a replacement for testing in required orientation.

Other suggestions for document improvement: The standard is not meant to cover the drop test required to simulate shipping and handling related shock of electronic components or PCB assemblies.


Other shock conditions, such jesd22 Condition H Gs, 0. Suite Arlington, VA Fax: Additional accelerometer may also be mounted on the board assembly at or close to one of the support locations to ensure that the input pulse to the base plate is transmitted to the PCB without any distortion.

In case of non-daisy chain die, a mechanical dummy die must be used inside the package to simulate the actual structure of the package. The kesd22 and mounting locations of the base plate shall be selected such there is no relative movement between the drop table and any part of base plate during drop testing.

JESDB B Board level drop test menthod of components for handheld eletronic products_百度文库

Wherever necessary, additional test points within each net shall be incorporated for failure location identification. This plate will serve as the mounting structure for the PCB assemblies. All comments will be collected and dispersed to the appropriate committee s. The test board shall have a nominal thickness of 1.

This acceleration factor shall be reported with the test data. All routing and traces within and just outside the component footprint shall be done on layer 2 and layer 8 for area array packages and layer 1 and layer 8 for perimeter leaded packages. Ford Packaging Drop Te